This invention relates generally to phase locked loops, and more specifically to prevention of runaway in a phase locked loop.
A phase-locked loop (PLL) is a closed-loop feedback control system that generates and outputs a signal in relation to the frequency and phase of an input signal. The PLL responds to both the frequency and the phase of the input signal and automatically raises or lowers the frequency of a controlled oscillator until it matches the input signal in both frequency and phase.
FIG. 1 illustrates a block diagram of a PLL 100. The PLL 100 comprises a phase-frequency indicator (PFD) 102, a charge pump 105, a loop filter 107, a voltage controller oscillator (VCO) 109, and a divider 111. The PFD 102 receives an input clock signal 101 from an input clock (not shown) and a feedback signal 112 from divider 111. The PFD 103 will either output an UP signal 103 or a DOWN signal 104 to the charge pump 105 based on the difference in frequency between input clock signal 101 and feedback signal 112. Based on the UP 103 or DOWN 104 signal provided to charge pump 105, the charge pump 105 outputs a charge pump voltage 106 to the loop filter 107. The loop filter 107 filters the charge pump voltage 106 to eliminate any noise or distortion before passing control voltage 108 to the VCO 109. Based on the control voltage 108, the VCO 109 may increase or decrease the frequency of the VCO's output signal, and output that frequency at PLL output 110.
The PLL 100 may operate in a steady-state (locked) or transient (unlocked) condition. When the PLL is in steady-state operation, the PLL output 110 from VCO 109 has a frequency that is N times higher than the frequency of the input clock signal 101 received by the PFD. The multiple N is the divisor used by divider 111. Thus, in lock, the feedback signal 112 input to the PFD 102 should have about the same frequency as the input clock signal 101; minor adjustments may be made using UP signal 103 and DOWN signal 104 accordingly.
Generally, the PLL 100 may operate in the transient state when the PLL 100 is powering up and acquiring lock. The PLL 100 also may operate in transient state if a disturbance, such as a supply glitch or other noise, causes the PLL 100 to lose lock. In transient state, the PLL output 110 may have any value, either above or below the frequency of the input clock signal 101. To attempt to bring the PLL 100 into the locked state, the PLL 100 may adjust the operation of the VCO 109 in a direction that will bring the PLL into lock.
The VCO 109 may not start at a low frequency because the control voltage 108 is initialized to a low value, which may be below the oscillator threshold of the VCO 109. When the PLL 100 starts, the control voltage 108 is ramped up past the oscillator threshold, and a noise event is relied upon to start the VCO 109. However, if the VCO 109 has low loop gain, it may not receive a noise event sufficient to start the VCO 109 in time, causing the control voltage 108 to ramp all the way to the power rail before the PFD 102 receives a feedback signal 112. If the noise event that starts VCO 109 occurs after the control voltage 108 ramps up to the power rail, the VCO 109 starts out running as fast as it can, and the PLL 100 may be in a runaway state. Runaway occurs when the frequency of the signal at PLL output 110 from VCO 109 is so high that the divider 111 fails to respond to it correctly, causing the PLL 100 to malfunction. Divider 111 may output a feedback signal 112 that is either a corrupted signal or no signal at all. In this situation, the PFD 102 may see signal transitions in input clock signal 101, but few or not transitions in feedback signal 112 from divider 111. The PFD 102 may mistakenly interpret this situation to be one in which the frequency at PLL output 110 is too low instead of too high. Consequently, instead of activating DOWN signal 104 to charge pump 105 to decrease the frequency of VCO 109, the PFD may actually activate the UP signal 103 to the charge pump 105, causing the frequency of VCO 109 to increase further until it plateaus at the maximum possible operating frequency.